The present invention relates to transistor gate stacks in integrated circuits, and more particularly to preventing degradation of gate dielectrics during processing.
In contemporary fabrication of integrated circuits, the metal-oxide-semiconductor field-effect transistor (MOSFET) has long been the most important device. Conductive gate material is formed over a gate dielectric (typically silicon dioxide), which in turn overlies a semiconductor substrate (typically single-crystal silicon).
The use of doped polycrystalline silicon (polysilicon, or poly for short) for MOSFET gate electrodes has entailed many advantages over purely metal gates, such as aluminum. Several advantages derive from the high melting point of polysilicon as compared to aluminum. Aluminum gates, for example, would have to be formed after high temperature dopant implantation and drive steps. Aluminum deposited after source/drain formation could be misaligned from the MOSFET channel, leading to parasitic gate/drain or gate/source overlap capacitance. By comparison, polysilicon gates can serve as a mask for doping source and drain regions, creating channels which are self-aligned to the gate. Additionally, unlike metals deposited directly over gate oxide, polysilicon will not react with the gate oxide, nor does it cause excessive dopant depletion. Because polysilicon gates can be formed prior to many high temperature steps, including glass reflow, the polysilicon deposited for the gate electrode may also function as an interconnect. For example, dynamic random access memory (DRAM) word lines may be etched from the polysilicon layer deposited for the gates (often referred to in the industry as xe2x80x9cpoly-1xe2x80x9d).
Unfortunately, polysilicon resistivity is considerably higher than that of aluminum or other metals. Additionally, efforts to increase circuit density by scaling down device dimensions lead to polysilicon lines of decreasing width, which in turn leaves a small cross-sectional line area through which to conduct current. High polysilicon resistivity, combined with small line width, results in a high overall interconnect resistance, entailing greater power consumption, long propagation delays and slower access speeds. As integrated circuits are scaled down, access speed becomes a critical issue so methods of reducing of gate/interconnect resistivity are required.
In pursuit of lower overall gate resistance, highly conductive layers (e.g., metal, metal silicide, and/or metal nitride) have been implemented over the gate polysilicon, thus lowering the overall resistivity of the interconnect lines while retaining the gate integrity provided by polysilicon. Typically, a layer of metal silicide (such as WSix or TiSix) is formed over the polysilicon. Such as silicide/polysilicon composite structure is often referred to as a xe2x80x9cpolycide.xe2x80x9d A metal layer may overlie the metal silicide, reducing resistivity even further, though many prior art gate structures lack the pure metal layer. Alternatively, a metal layer may also be deposited directly over the polysilicon, without the intervening metal silicide, depending upon stress and adhesion factors. A dielectric capping layer generally overlies the conductive layers of the gate stack.
FIG. 1 illustrates a typical gate stack 10 overlying a semiconductor substrate 20 prior to patterning. The illustrated stack includes a protective cap layer 12 (comprising, e.g., silicon nitride), a silicide layer (e.g., WSix), and a conductively doped polysilicon layer 16, all overlying a gate oxide 18 which has been grown out of a single crystal silicon substrate 20. After the layers which make up the gate stack 10 have been formed, gate structures must be patterned in accordance with an integrated circuit design (e.g., a dynamic random access memory, or DRAM, array).
FIG. 2 illustrates the result of patterning. After a resist mask 24 is formed by standard photolithographic processes, the stack 10 is etched through, thus producing a gate electrode 26 comprised of patterned gate polysilicon 28, silicide 30, and dielectric cap 32 straps, as shown. In general, anisotropic etches are utilized to create vertical profiles on gate structures 26, although the particulars may vary depending upon the stack materials. Typical etch chemistries include fluorine- or chlorine-based plasmas.
A high quality gate insulator is required for the reliable operation of the MOSFET device and of the circuit employing the MOSFET. Susceptibility to hot carrier effects and consequent charge trapping, high defect densities, silicon-oxide interface states, pinholes and oxide thinning can all cause punch-through or tunneling current leakage. In turn, junction leakage results in increased threshold voltage and unreliable circuit operation. For a variety of reasons, the processes involved in depositing the various gate stack layers and in patterning the gates, tends to degrade the quality of the gate oxide 18 underlying the patterned gate 26. For example, exposure to fluorine ions can damage oxide bonds within the gate oxide 18, creating charge trap sites. As fluorine and other contaminants have a tendency to diffuse through polysilicon, such gate oxide damage can penetrate even below the patterned gate stack 26. As a result, the gate dielectric 18 must either be made thicker (entailing greater power consumption) or early breakdown will occur.
Accordingly, a need exists for gate fabrication processes and structures which permit low overall resistance at the gate level while maintaining high quality gate dielectric compositions.
In accordance with one aspect of the present invention, a gate stack in an integrated transistor includes a gate dielectric overlying a semiconductor substrate, a first silicon layer overlying the gate dielectric, and a conductive layer directly overlying silicon layer. A nitrogen-containing second silicon layer is interposed between the first silicon layer and the conductive layer.
In accordance with another aspect of the present invention, an integrated circuit includes a semiconductor substrate, a dielectric layer overlying the substrate, a conductive silicon layer overlying the dielectric layer, and a metal silicide overlying the silicon layer. A non-metallic barrier layer is interposed between the metal silicide layer and the silicon layer. While the barrier layer electrically connects the metal silicide and the silicon layer, it also inhibits diffusion of impurities between those layers.
In accordance with another aspect of the present invention, a gate stack in an integrated circuit includes a polysilicon gate layer and a silicon-rich silicon nitride layer directly overlying the gate layer.
In accordance with another aspect of the present invention, an integrated circuit has a gate stack, including a conductive silicon gate layer, a silicon-based conductive barrier layer directly overlying the gate layer, and a metallic strap directly overlying the barrier layer.
In accordance with another aspect of the present invention, a process for forming an integrated circuit on a semiconductor substrate includes forming a silicon layer over the substrate. Nitrogen is incorporated into an upper portion of the silicon layer, such that the upper portion includes nitrogen to silicon in a ratio of less than 4:3. A metallic layer is deposited over the silicon layer by chemical vapor deposition.
In accordance with another aspect of the present invention, a method of forming a gate stack for an integrated transistor includes forming a gate silicon layer over a gate channel region in a semiconductor substrate. An upper portion of the gate silicon is then implanted with a non-conducting impurity.
In accordance with another aspect of the present invention, a method of forming a gate stack over a semiconductor substrate includes forming a gate dielectric directly over the substrate. A silicon source gas is flowed over the gate dielectric, thereby forming a first silicon layer directly over the gate dielectric. While continuing to flow the silicon source gas, a nitrogen source gas is flowed, thereby forming a second silicon layer directly over the first silicon layer.